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[Other resource] cf_vhdl

Description: CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.
Platform: | Size: 700616 | Author: gbh | Hits:

[Embeded-SCM Develop] PC48F0P0VB00_INTEL_1653358

Description: Intel StrataFlash® Embedded Memory(P30)
Platform: | Size: 1154710 | Author: wangxin | Hits:

[VHDL-FPGA-Verilog] cf_vhdl

Description: CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification. -CF VHDLThe CF+ Design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.
Platform: | Size: 700416 | Author: gbh | Hits:

[Embeded-SCM Develop] PC48F0P0VB00_INTEL_1653358

Description: Intel StrataFlash® Embedded Memory(P30) -Intel StrataFlash
Platform: | Size: 1154048 | Author: wangxin | Hits:

[ARM-PowerPC-ColdFire-MIPS] JFlash

Description: 目标平台：PXA255 Flash类型：Intel StrataFlash P30 16位 使用简介： 1、 解压附件，将目录复制到D:\JFlash下，可以看到目录Jflash和GIVEIO； 2、 安装GIVEIO，连接Jtag线到目标板； 3、 使用Jflash进行烧写；-Target platform: PXA255 Flash Type: Intel StrataFlash P30 16 Wei Use Description: 1, extract attachments, the directory to D: \ JFlash, you can see the directory Jflash and GIVEIO 2, installation GIVEIO, connect Jtag cable to the target board 3, using Jflash for Shao Xie
Platform: | Size: 140288 | Author: | Hits:

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